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january 2007 hys64d64020hbdl?5?c hys64d64020gbdl?5?c hys64d64020hbdl?6?c hys64d64020gbdl?6?c 200-pin small outline dual -in-line memory modules so-dimm ddr sdram internet data sheet rev. 1.21
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules qag_techdoc_rev400 / 3.2 qag / 2006-08-07 2 03292006-f1ib-1i3e hys64d64020hbdl?5?c, hys64d64020gbdl?5?c, hys64d64020hbdl?6?c, hys64d64020gbdl?6?c revision history: 2007-01, rev. 1.21 page subjects (major chang es since last revision) all qimonda update all adapted internet edition previous revision: 2005-09, rev. 1.2
internet data sheet rev. 1.21, 2007-01 3 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 1overview this chapter lists all main features of the product fam ily hys64d64020[h/g]bd l?[5/6]?c and the ordering information. 1.1 features ? non-parity 200-pin small outline dual-in-line memory modules ?two ranks 64m 64 organization ? jedec standard double data rate synchronous drams (ddr sdram) ? single +2.5 v ( 0.2 v) power supply and single +2.6 v ( 0.1 v) power supply for ddr400 ? built with 256 mbit ddr sdrams organised as 8 in p?tfbga?60 packages ? programmable cas latency, burst length, and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? ras-lockout supported t rap = t rcd ? all inputs and outputs sstl_2 compatible ? serial presence detect with e 2 prom ? jedec standard form factor: 67.60 mm 31.75 mm 3.80 mm ? gold plated contacts table 1 performance part number speed code ?5 ?6 unit speed grade component ddr400b ddr333b ? module pc3200?3033 pc2700?2533 ? max. clock frequency @cl3 f ck3 200 166 mhz @cl2.5 f ck2.5 166 166 mhz @cl2 f ck2 133 133 mhz
internet data sheet rev. 1.21, 2007-01 4 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 1.2 description the hys64d64020hbdl?5?c and hys64d64020gbdl?5? c are industry standard 200-pin small outline dual-in-line memory modules (so-dimms) organized as 64m 64. the memory array is designed with double data rate synchronous drams (ddr sdram). a variety of decoupling capacitors are mounted on the pc board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. table 2 ordering information table 3 ordering information for rohs compliant products notes 1. all part numbers end with a place code designating the silicon-die revision. reference information available on request. example: hys64d32020gdl-6-b, indicating rev. b dies are used for sdram components. 2. the compliance code is printed on the module labels describin g the speed sort (for example ?pc2700?), the latencies and spd code definition (for ex ample ?2033?0? means cas latency of 2.0 clocks, rcd 1) latency of 3 clocks, row precharge latency of 3 clocks, and jedec spd code definiton version 0), and the raw card used for this module. type compliance code description sdram technology pc3200 (cl=3.0) hys64d64020gbdl?5?c pc3200s?3033?1?z two ranks 512 mb so-dimm 32 mbit ( 8) pc2700 (cl=2.5) hys64d64020gbdl?6?c pc2700s?2533?0?z two ranks 512 mb so-dimm 32 mbit ( 8) product type 1) 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in elec trical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. compliance code descri ption sdram technology pc3200 (cl=3.0) hys64d64020hbdl?5?c pc3200s?3033?1?z two ranks 512 mb so-dimm 32 mbit ( 8) pc2700 (cl=2.5) hys64d64020hbdl?6?c pc2700s?2533?0?z two ranks 512 mb so-dimm 32 mbit ( 8) 1) rcd: row-column-delay
internet data sheet rev. 1.21, 2007-01 5 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 2 pin configuration the pin configuration of the unbuffered small outline ddr sdram dimm is listed by function in table 4 (184 pins). the abbreviations used in columns pin and buffer type are explained in table 5 and table 6 respectively. the pin numbering is depicted in figure 1 . table 4 pin configuration of so-dimm pin# name pin type buffer type function clock signals 35 ck0 i sstl clock signal 160 ck1 i sstl clock signal 89 ck2 i sstl clock signal note: ecc type module nc nc ? note: non-ecc type module 37 ck0 i sstl complement clock 158 ck1 i sstl complement clock 91 ck2 i sstl complement clock note: ecc type module nc nc ? note: non-ecc type module 96 cke0 i sstl clock enable rank 0 95 cke1 i sstl clock enable rank 1 note: 2-rank module nc nc ? note: 1-rank module control signals 121 s0 i sstl chip select rank 0 122 s1 i sstl chip select rank 1 note: 2-ranks module nc nc ? note: 1-rank module 118 ras i sstl row address strobe 120 cas i sstl column address strobe 119 we i sstl write enable address signals 117 ba0 i sstl bank address bus 1:0 116 ba1 i sstl
internet data sheet rev. 1.21, 2007-01 6 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 112 a0 i sstl address bus 11:0 111 a1 i sstl 110 a2 i sstl 109 a3 i sstl 108 a4 i sstl 107 a5 i sstl 106 a6 i sstl 105 a7 i sstl 102 a8 i sstl 101 a9 i sstl 115 a10 i sstl ap i sstl 100 a11 i sstl 99 a12 i sstl address signal 12 note: module based on 256 mbit or larger dies nc nc ? note: 128 mbit based module 123 a13 i sstl address signal 13 note: 1 gbit based module nc nc ? note: module based on 512 mbit or smaller dies data signals 5 dq0 i/o sstl data bus 63:0 7 dq1 i/o sstl 13 dq2 i/o sstl 17 dq3 i/o sstl 6 dq4 i/o sstl 8 dq5 i/o sstl 14 dq6 i/o sstl 18 dq7 i/o sstl 19 dq8 i/o sstl 23 dq9 i/o sstl 29 dq10 i/o sstl 31 dq11 i/o sstl 20 dq12 i/o sstl 24 dq13 i/o sstl pin# name pin type buffer type function
internet data sheet rev. 1.21, 2007-01 7 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 30 dq14 i/o sstl data bus 63:0 32 dq15 i/o sstl 41 dq16 i/o sstl 43 dq17 i/o sstl 49 dq18 i/o sstl 53 dq19 i/o sstl 42 dq20 i/o sstl 44 dq21 i/o sstl 50 dq22 i/o sstl 54 dq23 i/o sstl 55 dq24 i/o sstl 59 dq25 i/o sstl 65 dq26 i/o sstl 67 dq27 i/o sstl 56 dq28 i/o sstl 60 dq29 i/o sstl 66 dq30 i/o sstl 68 dq31 i/o sstl 127 dq32 i/o sstl 129 dq33 i/o sstl 135 dq34 i/o sstl 139 dq35 i/o sstl 128 dq36 i/o sstl 130 dq37 i/o sstl 136 dq38 i/o sstl 140 dq39 i/o sstl 141 dq40 i/o sstl 145 dq41 i/o sstl 151 dq42 i/o sstl 153 dq43 i/o sstl 142 dq44 i/o sstl 146 dq45 i/o sstl 152 dq46 i/o sstl 154 dq47 i/o sstl 163 dq48 i/o sstl 165 dq49 i/o sstl 171 dq50 i/o sstl 175 dq51 i/o sstl 164 dq52 i/o sstl 166 dq53 i/o sstl pin# name pin type buffer type function
internet data sheet rev. 1.21, 2007-01 8 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 172 dq54 i/o sstl data bus 63:0 176 dq55 i/o sstl 177 dq56 i/o sstl 181 dq57 i/o sstl 187 dq58 i/o sstl 189 dq59 i/o sstl 178 dq60 i/o sstl 182 dq61 i/o sstl 188 dq62 i/o sstl 190 dq63 i/o sstl 71 cb0 i/o sstl check bit 0 note: ecc type module nc nc ? note: non-ecc module 73 cb1 i/o sstl check bit 1 note: ecc type module nc nc ? note: non-ecc module 79 cb2 i/o sstl check bit 2 note: ecc type module nc nc ? note: non-ecc module 83 cb3 i/o sstl check bit 3 note: ecc type module nc nc ? note: non-ecc module 72 cb4 i/o sstl check bit 4 note: ecc type module nc nc ? note: non-ecc module 74 cb5 i/o sstl check bit 5 note: ecc type module nc nc ? note: non-ecc module 80 cb6 i/o sstl check bit 6 note: ecc type module nc nc ? note: non-ecc module 84 cb7 i/o sstl check bit 7 note: ecc type module nc nc ? note: non-ecc module pin# name pin type buffer type function
internet data sheet rev. 1.21, 2007-01 9 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 11 dqs0 i/o sstl data strobes 7:0 25 dqs1 i/o sstl 47 dqs2 i/o sstl 61 dqs3 i/o sstl 133 dqs4 i/o sstl 147 dqs5 i/o sstl 169 dqs6 i/o sstl 183 dqs7 i/o sstl 77 dqs8 i/o sstl data strobe 8 note: ecc type module nc nc ? note: non-ecc module 12 dm0 i sstl data mask 7:0 26 dm1 i sstl 48 dm2 i sstl 62 dm3 i sstl 134 dm4 i sstl 148 dm5 i sstl 170 dm6 i sstl 184 dm7 i sstl 78 dm8 i sstl data mask 8 note: ecc type module nc nc ? note: non-ecc module eeprom 195 scl i cmos serial bus clock 193 sda i/o od serial bus data 194 sa0 i cmos slave address select bus 2:0 196 sa1 i cmos 198 sa2 i cmos power supplies 1,2 v ref ai ? i/o reference voltage 197 v ddspd pwr ? eeprom power supply pin# name pin type buffer type function
internet data sheet rev. 1.21, 2007-01 10 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 9,10,21, 22, 33, 34, 36, 45, 46, 57, 58, 69, 70, 81, 82, 92, 93, 94, 113, 114, 131, 132, 143, 144, 155, 156, 157, 167, 168, 179, 180, 191, 192 v dd pwr ? power supply pin# name pin type buffer type function
internet data sheet rev. 1.21, 2007-01 11 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 3,4, 15, 16, 27, 28, 38, 39, 40, 51, 52, 63, 64, 75, 76, 87, 88, 90, 103, 104, 125, 126, 137, 138, 149, 150, 159, 161, 162, 173, 174, 185, 186 v ss gnd ? ground plane other pins 199 v ddid ood v dd identification 85, 86, 97, 98, 124, 200 nc nc ? not connected pin# name pin type buffer type function
internet data sheet rev. 1.21, 2007-01 12 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules table 5 abbreviations for pin type table 6 abbreviations for buffer type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectio nal input/output signal. ai input. analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminalted logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operat ional states, active low and tristate, and allows multiple devices to share as a wire-or.
internet data sheet rev. 1.21, 2007-01 13 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules figure 1 pin configuration diagram 200-pin so-dimm table 7 address format density organization memory ranks sdrams # of sdrams # of row/bank/ columns bits refresh period interval 512mb 64m 64 2 32m 8 16 13/2/10 8k 64 ms 7.8 ms 0 3 3 ' 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 5 ( ) ' 4 9 ' ' ' 4 ' 4 9 ' ' ' 0 ' 4 9 ' ' ' 4 ' 0 ' 4 ' 4 ' 4 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 0 ' 4 ' 4 ' 4 & % 1 & & % 1 & & % 1 & & . ( $ $ $ % $ & $6 1 & ' 4 ' 4 ' 4 ' 0 ' 4 & . ' 4 ' 4 ' 4 ' 0 ' 4 6 $ 1 & 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 ' 4 9 ' ' ' 0 ' 4 & % 1 & ' 0 1 & 9 ' ' 1 & 9 6 6 9 ' ' 1 & $ $ $ 9 ' ' 5 $6 6 1 & ' 4 ' 0 ' 4 ' 4 ' 4 & . ' 4 ' 0 ' 4 ' 4 9 6 6 ' 4 6 $ 6 $ 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 5 ( ) ' 4 9 ' ' ' 4 ' 4 9 ' ' ' 4 6 ' 4 9 ' ' & . ' 4 ' 4 6 ' 4 ' 4 ' 4 & . 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 6 ' 4 ' 4 ' 4 & % 1 & & % 1 & & % 1 & & . 1 & & . ( 1 & $ 1 & $ $ $ $3 : ( $ 1 & ' 4 ' 4 ' 4 ' 4 6 ' 4 ' 4 ' 4 ' 4 ' 4 6 ' 4 6 & / 9 ' ' , ' 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 9 ' ' ' 4 ' 4 9 ' ' ' 4 6 ' 4 9 ' ' & % 1 & ' 4 6 1 & 9 ' ' 1 & & . 1 & 9 ' ' 1 & $ $ $ 9 ' ' % $ 6 ' 4 ' 4 6 ' 4 ' 4 ' 4 9 ' ' ' 4 ' 4 6 ' 4 ' 4 9 6 6 ' 4 6 ' $ 9 ' ' 6 3 ' 9 ' ' 9 ' ' 9 ' ' 9 6 6 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 ' ' 9 6 6 ) 5 2 1 7 6 , ' ( % $ & . 6 , ' ( 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 6 6 9 ' '
internet data sheet rev. 1.21, 2007-01 14 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 3 electrical characteristics this chapter lists the el ectrical characteristics. 3.1 operating conditions this chapter contains the operating conditions tables. table 8 absolute maximum ratings attention: permanent damage to the device may occur if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation should be rest ricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause ir reversible damage to the integrated circuit. parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg -55 ? +150 c? power dissipation (per sdram component) p d?1?w? short circuit output current i out ?50?ma?
internet data sheet rev. 1.21, 2007-01 15 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules table 9 electrical characteristics and dc operating conditions parameter symbol values unit note 1) / test condition 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v; v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400); min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz device supply voltage v dd 2.5 2.6 2.7 v f ck >166mhz 2) 2) ddr400 conditions apply for all clock frequencies above 166 mhz output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 3) 3) under all conditions, v ddq must be less than or equal to v dd . output supply voltage v ddq 2.5 2.6 2.7 v f ck >166mhz 2)3) eeprom supply voltage v ddspd 2.3 2.5 3.6 v ? supply voltage, i/o supply voltage v ss , v ssq 0?0v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 4) 4) peak to peak ac noise on v ref may not exceed 2% vref (dc). vref is also expected to track noise variations in v ddq . i/o termination voltage (system) v tt v ref ? 0.04 ? v ref + 0.04 v 5) 5) v tt is not applied directly to the device. v tt is a system supply for signal terminati on resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . input high (logic1) voltage v ih(dc) v ref + 0.15 ? v ddq + 0.3 v 6) 6) inputs are not recognized as valid until v ref stabilizes. input low (logic0) voltage v il(dc) ?0.3 ? v ref ? 0.15 v 5) input voltage level, ck and ck inputs v in(dc) ?0.3 ? v ddq + 0.3 v 5) input differential voltage, ck and ck inputs v id(dc) 0.36 ? v ddq + 0.6 v 5)7) 7) v id is the magnitude of the difference between the input level on ck and the input level on ck . vi-matching pull-up current to pull-down current vi ratio 0.71 ? 1.4 ? 8) 8) the ratio of the pull-up current to the pull-down current is s pecified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1. 0 v. for a given output, it represents the maximum difference b etween pull-up and pull-down drivers due to process variation. input leakage current i i ?2 ? 2 aany input 0v v in v dd ; all other pins not under test = 0 v 9) 9) values are shown per pin. output leakage current i oz ?5 ? 5 a dqs are disabled; 0 v v out v ddq 9) output high current, normal strength driver i oh ? ? ?16.2 ma v out = 1.95 v output low current, normal strength driver i ol 16.2 ? ? ma v out = 0.35 v
internet data sheet rev. 1.21, 2007-01 16 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 3.2 current specification and conditions table 10 i dd conditions parameter symbol operating current 0 one bank; active/ precharge; dq, dm, and dq s inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. i dd0 operating current 1 one bank; active/read/precharge; burs t length = 4; see component data sheet. i dd1 precharge power-down standby current all banks idle; power-down mode; cke v il,max i dd2p precharge floating standby current cs v ih,,min , all banks idle; cke v ih,min ; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current cs v ihmin , all banks idle; cke v ih,min ; v in = v ref for dq, dqs and dm; address and other control inputs stable at v ih,min or v il,max . i dd2q active power-down standby current one bank active; power-down mode; cke v ilmax ; v in = v ref for dq, dqs and dm. i dd3p active standby current one bank active; cs v ih,min ; cke v ih,min ; t rc = t ras,max ; dq, dm and dqs inputs cha nging twice per clock cycle; address and control inputs changing once per clock cycle. i dd3n operating current read one bank active; burst length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b; i out =0ma i dd4r operating current write one bank active; burst length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b i dd4w auto-refresh current t rc = t rfcmin , burst refresh i dd5 self-refresh current cke 0.2 v; external clock on i dd6 operating current 7 four bank interleaving with burst length = 4; see component data sheet. i dd7
internet data sheet rev. 1.21, 2007-01 17 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules table 11 i dd specification for hys64d64020[g/h]bdl?5?c product type hys64d64020gbdl?5?c hys64d64020hbdl?5?c unit note 1)2) 1) module i dd values are calculated on the basis of component i dd and can be measured differently according to dq loading capacity. 2) test condition for maximum values: v dd =2.7v, t a =10c organization 512mb 64 2 ranks ?5 symbol typ. max. i dd0 940 1150 ma 3) 3) the module i ddx values are calculated from the i ddx values of the component data sheet as follows: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 1100 1310 ma 4) 4) dq i/o ( i ddq ) currents are not included in the calculations (see note 1) ) i dd2p 480 580 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 320 450 ma 5) i dd2q 210 290 ma 5) i dd3p 610 720 ma 5) i dd3n 690 860 ma 5) i dd4r 1140 1390 ma 3)4) i dd4w 1140 1470 ma 3) i dd5 360 450 ma 3) i dd6 16 17.6 ma 5) i dd7 2020 2430 ma 3)4)
internet data sheet rev. 1.21, 2007-01 18 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules table 12 i dd specification for hys64d64020[g/h]bdl?6?c product type hys64d64020gbdl?6-? c hys64d64020hbdl?6?c unit note 1)2) 1) module i dd values are calculated on the basis of component i dd and can be measured differently according to dq loading capacity. 2) test condition for maximum values: v dd =2.7v, t a =10c organization 512mb 64 2 ranks ?6 symbol typ. max. i dd0 810 960 ma 3) 3) the module i ddx values are calculated from the i ddx values of the component data sheet as follows: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 930 1120 ma 3)4) 4) dq i/o ( i ddq ) currents are not included in the calculations (see note 1) ) i dd2p 400 480 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 270 380 ma 5) i dd2q 180 240 ma 5) i dd3p 510 610 ma 5) i dd3n 580 720 ma 5) i dd4r 970 1160 ma 3)4) i dd4w 1010 1240 ma 3) i dd5 300 380 ma 3) i dd6 16 17.6 ma 5) i dd7 1730 2080 ma 3)4)
internet data sheet rev. 1.21, 2007-01 19 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules table 13 ac timing - absolute specifications for pc3200 and pc2700 parameter symbol ?5 ?6 unit note 1) / test condition ddr400b ddr333 min. max. min. max. dq output access time from ck/ck t ac ?0.5 +0.5 ?0.7 +0.7 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock cycle time t ck 5 8 6 12 ns cl = 3.0 2)3)4)5) 6 12 6 12 ns cl = 2.5 2)3)4)5) 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) auto precharge write recovery + precharge time t dal ( t wr / t ck )+( t rp / t ck ) t ck 2)3)4)5)6) dq and dm input hold time t dh 0.4 ? 0.45 ? ns 2)3)4)5) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? ns 2)3)4)5)6) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.6 +0.6 ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.40 ns tfbga 2)3)4)5) write command to 1 st dqs latching transition t dqss 0.72 1.25 0.75 1.25 t ck 2)3)4)5) dq and dm input setup time t ds 0.4 ? 0.45 ? ns 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )min. ( t cl , t ch )ns 2)3)4)5) data-out high-impedance time from ck/ck t hz ? +0.7 ?0.7 +0.7 ns 2)3)4)5)7) address and control input hold time t ih 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? ns 2)3)4)5)9)
internet data sheet rev. 1.21, 2007-01 20 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules address and control input setup time t is 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) data-out low-impedance time from ck/ck t lz ?0.7 +0.7 ?0.7 +0.7 ns 2)3)4)5)7) mode register set command cycle time t mrd 2?2? t ck 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs t hp ? t qhs ns 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.50 ns tfbga 2)3)4)5) active to autoprecharge delay t rap t rcd ? t rcd ?ns 2)3)4)5) active to precharge command t ras 40 70e+3 42 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 55 ? 60 ? ns 2)3)4)5) active to read or write delay t rcd 15 ? 18 ? ns 2)3)4)5) average periodic refresh interval t refi ? 7.8 ? 7.8 s 2)3)4)5)10) auto-refresh to active/auto- refresh command period t rfc 65 ? 72 ? ns 2)3)4)5) precharge command period t rp 15 ? 18 ? ns 2)3)4)5) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active bank a to active bank b command t rrd 10 ? 12 ? ns 2)3)4)5) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5) write preamble setup time t wpres 0?0?ns 2)3)4)5)11) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)12) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) internal write to read command delay t wtr 2?1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) 1) 0 c t a 70 c ; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input refe rence level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 8) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v ih(ac) and v il(ac) . parameter symbol ?5 ?6 unit note 1) / test condition ddr400b ddr333 min. max. min. max.
internet data sheet rev. 1.21, 2007-01 21 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 9) these parameters guarantee device timing, but th ey are not necessarily tested on each device. 10) a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 11) the specific requirement is that dqs be valid (high,low, or some point on a valid transition) on or before this ck edge. a v alid transition is defined as monotonic and meeting the input slew rate specificationsof the device. w hen no writes were previously in progress on the bus, dqs will be transitioni ng from hi-z to logic low. if a previous write wa s in progress, dqs could be high, low at this time , depending on t dqss . 12) the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly.
internet data sheet rev. 1.21, 2007-01 22 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 4 spd codes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect. all values with xx in the table are module specific bytes which are defined during production. list of spd code tables ? table 14 ?spd codes for hys64d64020hbdl?5?c and hys64d64020gbdl?5?c? on page 22 ? table 15 ?spd codes for hys64d64020hbdl?6?c and hys64d64020gbdl?6?c? on page 25 table 14 spd codes for hys64d64020hbdl?5?c and hys64d64020gbdl?5?c product type hys64d64020gbdl?5?c hys64d64020hbdl?5?c organization 512mb 512mb 64 64 2 ranks ( 8) 2 ranks ( 8) label code pc3200s?30331 pc3200s?30331 jedec spd revision rev. 1.0 rev. 1.0 byte# description hex hex 0 programmed spd bytes in e 2 prom 80 80 1 total number of bytes in e 2 prom 08 08 2 memory type (ddr = 07h) 07 07 3 number of row addresses 0d 0d 4 number of column addresses 0a 0a 5 number of dimm ranks 02 02 6 data width (lsb) 40 40 7 data width (msb) 00 00 8 interface voltage levels 04 04 9 t ck @ cl max (byte 18) [ns] 50 50 10 t ac sdram @ cl max (byte 18) [ns] 50 50 11 error correction support 00 00 12 refresh rate 82 82 13 primary sdram width 08 08 14 error checking sdram width 00 00 15 t ccd [cycles] 01 01 16 burst length supported 0e 0e 17 number of banks on sdram device 04 04 18 cas latency 1c 1c 19 cs latency 01 01 20 write latency 02 02
internet data sheet rev. 1.21, 2007-01 23 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 21 dimm attributes 20 20 22 component attributes c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 60 60 24 t ac sdram @ cl max -0.5 [ns] 50 50 25 t ck @ cl max -1 (byte 18) [ns] 75 75 26 t ac sdram @ cl max -1 [ns] 50 50 27 t rpmin [ns] 3c 3c 28 t rrdmin [ns] 28 28 29 t rcdmin [ns] 3c 3c 30 t rasmin [ns] 28 28 31 module density per rank 40 40 32 t as, t cs [ns] 60 60 33 t ah, t ch [ns] 60 60 34 t ds [ns] 40 40 35 t dh [ns] 40 40 36 - 40 not used 00 00 41 t rcmin [ns] 37 37 42 t rfcmin [ns] 41 41 43 t ckmax [ns] 28 28 44 t dqsqmax [ns] 28 28 45 t qhsmax [ns] 50 50 46 not used 00 00 47 dimm pcb height 01 01 48 - 61 not used 00 00 62 spd revision 10 10 63 checksum of byte 0-62 0f 0f 64 manufacturer?s jedec id code (1) 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 69 manufacturer?s jedec id code (6) 51 51 70 manufacturer?s jedec id code (7) 00 00 product type hys64d64020gbdl?5?c hys64d64020hbdl?5?c organization 512mb 512mb 64 64 2 ranks ( 8) 2 ranks ( 8) label code pc3200s?30331 pc3200s?30331 jedec spd revision rev. 1.0 rev. 1.0 byte# description hex hex
internet data sheet rev. 1.21, 2007-01 24 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 71 manufacturer?s jedec id code (8) 00 00 72 module manufacturer location xx xx 73 part number, char 1 36 36 74 part number, char 2 34 34 75 part number, char 3 44 44 76 part number, char 4 36 36 77 part number, char 5 34 34 78 part number, char 6 30 30 79 part number, char 7 32 32 80 part number, char 8 30 30 81 part number, char 9 47 48 82 part number, char 10 42 42 83 part number, char 11 44 44 84 part number, char 12 4c 4c 85 part number, char 13 35 35 86 part number, char 14 43 43 87 part number, char 15 20 20 88 part number, char 16 20 20 89 part number, char 17 20 20 90 part number, char 18 20 20 91 module revision code 1x 1x 92 test program revision code xx xx 93 module manufacturing date year xx xx 94 module manufacturing date week xx xx 95 - 98 module serial number xx xx 99 - 127 not used 00 00 product type hys64d64020gbdl?5?c hys64d64020hbdl?5?c organization 512mb 512mb 64 64 2 ranks ( 8) 2 ranks ( 8) label code pc3200s?30331 pc3200s?30331 jedec spd revision rev. 1.0 rev. 1.0 byte# description hex hex
internet data sheet rev. 1.21, 2007-01 25 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules table 15 spd codes for hys64d64020hbdl?6?c and hys64d64020gbdl?6?c product type hys64d64020gbdl?6?c hys64d64020hbdl?6?c organization 512mb 512mb 64 64 2 ranks ( 8) 2 ranks ( 8) label code pc2700s?25330 pc2700s?25330 jedec spd revision rev. 0.0 rev. 0.0 byte# description hex hex 0 programmed spd bytes in e 2 prom 80 80 1 total number of bytes in e 2 prom 08 08 2 memory type (ddr = 07h) 07 07 3 number of row addresses 0d 0d 4 number of column addresses 0a 0a 5 number of dimm ranks 02 02 6 data width (lsb) 40 40 7 data width (msb) 00 00 8 interface voltage levels 04 04 9 t ck @ cl max (byte 18) [ns] 60 60 10 t ac sdram @ cl max (byte 18) [ns] 70 70 11 error correction support 00 00 12 refresh rate 82 82 13 primary sdram width 08 08 14 error checking sdram width 00 00 15 t ccd [cycles] 01 01 16 burst length supported 0e 0e 17 number of banks on sdram device 04 04 18 cas latency 0c 0c 19 cs latency 01 01 20 write latency 02 02 21 dimm attributes 20 20 22 component attributes c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 75 75 24 t ac sdram @ cl max -0.5 [ns] 70 70 25 t ck @ cl max -1 (byte 18) [ns] 00 00 26 t ac sdram @ cl max -1 [ns] 00 00 27 t rpmin [ns] 48 48 28 t rrdmin [ns] 30 30 29 t rcdmin [ns] 48 48
internet data sheet rev. 1.21, 2007-01 26 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 30 t rasmin [ns] 2a 2a 31 module density per rank 40 40 32 t as, t cs [ns] 75 75 33 t ah, t ch [ns] 75 75 34 t ds [ns] 45 45 35 t dh [ns] 45 45 36 - 40 not used 00 00 41 t rcmin [ns] 3c 3c 42 t rfcmin [ns] 48 48 43 t ckmax [ns] 30 30 44 t dqsqmax [ns] 28 28 45 t qhsmax [ns] 50 50 46 not used 00 00 47 dimm pcb height 00 00 48 - 61 not used 00 00 62 spd revision 00 00 63 checksum of byte 0-62 f8 f8 64 manufacturer?s jedec id code (1) 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 69 manufacturer?s jedec id code (6) 51 51 70 manufacturer?s jedec id code (7) 00 00 71 manufacturer?s jedec id code (8) 00 00 72 module manufacturer location xx xx 73 part number, char 1 36 36 74 part number, char 2 34 34 75 part number, char 3 44 44 76 part number, char 4 36 36 77 part number, char 5 34 34 78 part number, char 6 30 30 79 part number, char 7 32 32 product type hys64d64020gbdl?6?c hys64d64020hbdl?6?c organization 512mb 512mb 64 64 2 ranks ( 8) 2 ranks ( 8) label code pc2700s?25330 pc2700s?25330 jedec spd revision rev. 0.0 rev. 0.0 byte# description hex hex
internet data sheet rev. 1.21, 2007-01 27 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 80 part number, char 8 30 30 81 part number, char 9 47 48 82 part number, char 10 42 42 83 part number, char 11 44 44 84 part number, char 12 4c 4c 85 part number, char 13 36 36 86 part number, char 14 43 43 87 part number, char 15 20 20 88 part number, char 16 20 20 89 part number, char 17 20 20 90 part number, char 18 20 20 91 module revision code 1x 1x 92 test program revision code xx xx 93 module manufacturing date year xx xx 94 module manufacturing date week xx xx 95 - 98 module serial number xx xx 99 - 127 not used 00 00 product type hys64d64020gbdl?6?c hys64d64020hbdl?6?c organization 512mb 512mb 64 64 2 ranks ( 8) 2 ranks ( 8) label code pc2700s?25330 pc2700s?25330 jedec spd revision rev. 0.0 rev. 0.0 byte# description hex hex
internet data sheet rev. 1.21, 2007-01 28 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 5 package outlines this chapter contains the package outlines of the products. figure 2 package outline so-dimm l-dim-200-22 0.1 63.6 67.6 31.75 4 0.1 11.4 1 47.4 0.1 (2.4) 0.1 18.45 1.8 0.1 0.1 (2.45) 0.1 0.1 1 0.1 1.5 (2.7) 4 6 0.1 0.1 20 2 min. 3.8 max. 0.1 1 0.15 (2.15) (2.45) 0.05 1.8 (2.15) 199 200 2 gld09573 detail of contacts 0.25 -0.1 8 0.45 0.03 0.6 0.1 2.55 burnished, no burr allowed
internet data sheet rev. 1.21, 2007-01 29 03292006-f1ib-1i3e hys64d64020[h/g]bdl?[5/6]?c small outline ddr sdram modules 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 current specification and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table of contents
edition 2007-01 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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